Industry Research Report on DEX Research

AI and Computing Infrastructure: Industry History, Value Chain, and Challenges

Thu, 01 Oct 2026 21:45:00 +0800

Sources current to October 1, 2026. This report covers the chips, servers, data centers and cloud services used for AI training and inference. Financial figures retain each company’s reporting period and business scope. Supporting materials appear in a separate appendix outside Parts 1 to 4.

AI services depend on a chain of suppliers and operators that turn equipment into usable computing capacity. This report follows an order through that chain, traces how the industry developed, identifies representative companies, and examines the constraints on delivery and investment returns.

Part 1: Story

In September 2026, Dell reported results for the fiscal quarter ended July 31. AI-optimized server revenue was $16.4 billion, new orders totaled $60.9 billion, and the quarter ended with a $95 billion backlog.^[23] Revenue represents business recognized during the quarter, orders reflect newly booked demand, and backlog is the stock still awaiting delivery. Converting that backlog into revenue requires production and delivery to be completed.

Much has to happen between an order and a working installation. Server vendors need accelerators, memory and networking components to arrive, then must test the assembled systems. Customers need sites with suitable power and cooling. A delay at one stage can push back the deployment schedule. For the customer, receiving the equipment is only one step in the project.

Once a cluster is running, the operating questions change. Users care less about how many chips it contains than whether its answers are useful and arrive quickly enough. Service providers must handle more paid requests while meeting those expectations, because depreciation, electricity bills and staffing costs continue. The capabilities promised at purchase have to be delivered in everyday operation.

AI infrastructure connects businesses that can otherwise look quite different. Chip design, manufacturing, system delivery and cloud services all respond to the same underlying demand. Understanding the industry means following an order through to the point where computing capacity is used and customers continue paying for it. The formation of this value chain begins with much earlier changes in research and engineering.

Part 2: Industry History

1. From research questions to commercial experiments

In 1943, McCulloch and Pitts proposed a mathematical model of neural activity. In 1950, Alan Turing examined machine intelligence and introduced the ‘imitation game’. The term ‘artificial intelligence’ appeared in the 1955 proposal for the Dartmouth research project, which took place in the summer of 1956. The first question was whether ideas about intelligence could be turned into programs a computer could execute.^[1]

Early programs made progress on well-defined problems but often failed when faced with the complexity of the real world. In the 1970s, disappointed research expectations were followed by cuts in funding. Expert systems, which rose to prominence in the 1980s, encoded domain knowledge as rules but were subsequently constrained by maintenance costs and limited adaptability. Specialized Lisp computers also faced competition from cheaper general-purpose workstations. Both downturns exposed the distance between a technical demonstration and a commercially sustainable application.^[2]

In 1997, IBM’s Deep Blue defeated Garry Kasparov in a six-game match. It combined specialized search chips, parallel computing, evaluation functions and databases of chess games to solve a clearly defined problem. The principle of designing a system around a task can still be seen in later AI infrastructure.^[3]

2. GPUs and cloud computing improve access

GPUs can perform many similar operations at once, making them well suited to much of the computation in neural networks. NVIDIA introduced the CUDA architecture in 2006 and made related development tools available in 2007. Researchers gained not only faster chips but also programming tools they could put to work. Around the same time, AWS launched its S3 storage and EC2 computing services in 2006, allowing developers to rent infrastructure.^[4]^[5]

AlexNet provided a clear example of the change in 2012. The individual network described in the paper took about five to six days to train on two GTX 580 GPUs. The team’s ensemble of models achieved a top-5 test error rate of 15.3% in the ImageNet competition, compared with 26.2% for the runner-up. This error rate measures the share of cases in which the correct category did not appear among the five highest-ranked answers. GPUs, labeled data, network design and training methods all contributed to the breakthrough.^[6]

3. Larger training runs change system design

In 2018, OpenAI analyzed large training runs carried out since 2012. It found that the amount of compute used in the largest runs in its sample had doubled roughly every 3.4 months, increasing by more than 300,000 times overall. This was a historical change in resources devoted to training. It was not a growth rate for model capabilities, and it cannot simply be extrapolated to the present.^[7]

Hardware and algorithms were both changing. NVIDIA introduced Tensor Cores with its Volta architecture in 2017 to accelerate matrix operations. Google’s first-generation TPU, deployed from 2015, was designed primarily for inference: applying an already-trained model to new inputs. The 2017 Transformer paper demonstrated greater training parallelism in its machine-translation experiments and provided an architectural foundation for later language models.^[8]^[9]^[10]

GPT-3, introduced in 2020, had 175 billion parameters. ChatGPT’s release in 2022 brought conversational models to a much wider audience. Demand acquired an additional dimension: systems had to handle a continuous stream of user requests as well as complete training runs.^[11]

4. Computing becomes a data center engineering problem

Meta’s 2024 Llama 3 report described using up to approximately 16,000 H100 GPUs to train its 405-billion-parameter model and discussed networking, storage and fault recovery in detail. As the number of machines grows, communication delays and downtime become more costly.^[12]

Cooling must keep pace with increasing system density. The GB200 NVL72 uses a liquid-cooled rack, while the H100 product range still includes air-cooled configurations. The choice depends on power consumption and deployment conditions. Software also changes how efficiently equipment is used: the PagedAttention study demonstrated that better GPU memory management could improve inference throughput under the conditions tested.^[13]^[14]

Power supply further constrains where a project can be built and when it can enter service. In its 2026 report, the International Energy Agency estimated global data center electricity consumption at approximately 485 terawatt-hours in 2025 and forecast approximately 950 terawatt-hours in 2030. These figures include non-AI uses. Operators must then answer a set of practical questions: when will the equipment go live, how many customers can it serve, and how long will it take to recover the investment?^[15]

Part 3: Value Chain

INDUSTRY MAP

The AI computing infrastructure value chain

Follow the capabilities needed to turn chips into usable computing services.

Read the full text outline

AI computing infrastructure
- Upstream · Design and components
  - Accelerators and software
    - GPUs, development tools and model execution
    - Representative companies
      - NVIDIA
      - AMD
      - Huawei
  - Cloud provider chips
    - Specialized accelerators for cloud workloads
    - Representative companies
      - AWS · Trainium
      - Google · TPU
  - Fabrication and advanced packaging
    - Wafer production and system integration
    - Representative companies
      - TSMC
      - ASE
  - HBM memory
    - Data capacity and transfer bandwidth
    - Representative companies
      - SK hynix
      - Micron
      - Samsung
- Midstream · Systems and facilities
  - Networking and interconnects
    - Communication between servers and computing nodes
    - Representative companies
      - NVIDIA
      - Broadcom
  - Servers and integration
    - Assembly, testing and delivery of complete systems
    - Representative companies
      - Dell
      - Supermicro
  - Power and cooling
    - Power distribution, thermal management and site readiness
    - Representative companies
      - Vertiv
      - Schneider Electric
- Downstream · Computing services
  - Cloud computing services
    - Capacity, service availability and cluster operations
    - Representative companies
      - AWS
      - Microsoft Azure
      - Google Cloud
      - CoreWeave
  - Customer uses
    - Model training
    - Inference and business applications

DEX editorial map based on Part 3 and the supporting appendix. Company examples are illustrative and may span several stages. Branches group business roles; they do not establish supplier contracts, market shares or an exhaustive list.

Sources: NVIDIA · computing and networking business · TSMC · CoWoS advanced packaging · Dell · AI server revenue and delivery pipeline · IEA · energy and infrastructure constraints. Reviewed 2026-10-01.

1. Working back from the customer’s bill

The value chain ends with the user of computing capacity. A business might rent GPUs by the hour or pay for model services according to usage. At sufficient scale, it may build its own cluster. Cloud providers collect service fees and spend a portion on servers, networking, electricity and operations. Server suppliers buy accelerators, memory and other components, while chip designers purchase manufacturing services from foundries and packaging providers. This is a simplified account of a typical division of work. Actual contracts may also involve large customers buying components directly and commissioning their integration.

The same end-customer demand generates revenue for several companies along the chain. Chip sales, server sales and cloud revenue therefore cannot simply be added together to calculate market size. When examining a particular stage, identifying the customer, the product or service delivered and the point at which revenue is recognized is more useful than starting with a single figure for the entire industry.

The table identifies representative companies by what they deliver. A company may participate at several stages; the list is not a market-share ranking.

Value chain stage	Representative companies	Business role and sources
Accelerators and software	NVIDIA , AMD , Huawei	NVIDIA supplies GPUs and CUDA; AMD offers Instinct products; Huawei provides the Ascend platform and CANN.^[4]^[18]^[19]^[27]
Cloud provider chips	AWS , Google	Develop Trainium and TPU respectively, configuring compute for internal and customer workloads.^[21]^[22]
Fabrication and advanced packaging	TSMC , ASE	TSMC provides wafer fabrication and CoWoS; ASE supplies advanced packaging including 2.5D/3D integration.^[16]^[29]
HBM memory	SK hynix , Micron , Samsung	Supply high-bandwidth memory, providing accelerators with data capacity and transfer bandwidth.^[17]^[30]^[31]
Networking and interconnects	NVIDIA , Broadcom	Supply data center networking products and chips that connect servers and computing nodes.^[18]^[20]
Servers and integration	Dell , Supermicro	Integrate accelerators and other components into AI servers, with air-cooled and liquid-cooled system formats.^[23]^[32]
Power and cooling	Vertiv , Schneider Electric	Supply power, thermal management and supporting data center infrastructure.^[24]^[33]
Cloud computing services	AWS , Microsoft Azure , Google Cloud , CoreWeave	Deliver computing capacity and related services to customers and operate the underlying clusters.^[5]^[25]^[26]^[34]

2. Chip design and software

Accelerator design determines how computing units, on-chip memory and interconnects work together. Software determines whether models can use those resources. CUDA offers one way to understand this relationship: development tools, libraries and accumulated code affect the engineering work required to move to different hardware.^[4] On that basis, this report argues that a chip should be assessed not only on performance and price, but also on the time needed to migrate models, debug them and achieve stable operation.

General-purpose GPUs can accommodate changing models and customer requirements. Large cloud providers are also in a position to develop specialized chips for more clearly defined workloads. AWS announced general availability of Trainium3 UltraServers in December 2025. Google introduced the TPU 8t and 8i for different workloads in April 2026. The former was an availability announcement; the latter was a product announcement. Neither establishes how many systems have actually been deployed.^[21]^[22]

This creates two different commercial choices: selling chips and using chips to provide services. Whether an in-house chip pays off depends on how widely development costs can be spread, as well as performance, utilization and operating costs after migration. Cloud providers have an incentive to reduce the cost of serving each unit of demand. External customers are more concerned with whether their workloads run successfully.

3. Manufacturing advanced packaging and memory

Once a chip is designed, it must pass through wafer fabrication, packaging and testing. Advanced packaging is taking on more work. TSMC’s CoWoS, for example, connects logic chips and high-bandwidth memory within the same packaging system. In its second-quarter 2026 earnings call, TSMC said packaging capacity remained tight. More wafer supply does not automatically mean complete accelerators can be delivered on time.^[16]

HBM is high-bandwidth memory placed close to the computing chip. Capacity determines how much data it can hold, while bandwidth affects how quickly data moves. One cannot substitute for the other. Micron’s published specifications for its 12-high HBM4 product, for example, list 36 GB of capacity and bandwidth exceeding 2.8 TB/s. These are component specifications; they cannot be converted directly into the amount of text a server generates per second.^[17]

Constraints at this stage travel through the supply chain. Delays in computing chips, HBM or packaging can each hold up system shipments. Capacity expansion, meanwhile, requires upfront spending. The corresponding additional revenue generally cannot be recognized until the new capacity is ready and products have been delivered. Assessing business conditions therefore requires looking at demand, construction progress and yields together, rather than relying on expansion announcements alone.

4. Networks and server integration

Large training clusters must exchange data between computing nodes while continuously reading training material from storage.^[12] Assessing a system therefore requires measuring how much time is spent on communication and data access. A single chip’s peak computing performance does not capture these issues.

Server vendors and system integrators combine accelerators, CPUs, memory, networking and cooling into deliverable products. They also handle testing, deployment and after-sales service. Revenue can grow rapidly, but the funding needed for procurement, inventory commitments and delivery obligations rise with it.

5. Power cooling and cloud operations

Data centers need power distribution, backup power, cooling equipment and routine maintenance. Buying servers does not by itself provide usable computing capacity: sites, grid connections and installation must also be ready. Vertiv supplies infrastructure including power and thermal-management systems. It reported approximately $3.274 billion in sales in the second quarter of 2026. That figure indicates the scale of one supplier’s business; it cannot all be classified as revenue from liquid cooling for AI.^[24]

Once systems are operating, utilization and pricing become central. Training customers may occupy large amounts of equipment for a defined period, while inference services must respond to changing request volumes and latency requirements. Under the same requirements for answer quality and waiting time, the number of requests each machine can handle is a measure of efficiency closer to what operators need. Software optimization and standardized testing provide ways to make such comparisons.^[14]^[28]

The operating economics can be expressed as a straightforward calculation: service revenue must cover equipment depreciation, financing, electricity, premises, networking and operating costs. Even as new chips become faster, older equipment may still serve less demanding tasks. But falling rental prices or low utilization will lengthen the payback period. End customers’ willingness to pay determines whether expansion further up the chain can produce recurring revenue.

Part 4: Industry Challenges

1. Supply constraints and delivery schedules

Advanced manufacturing, packaging, memory and grid connections constrain different stages of delivery. TSMC’s disclosure of tight packaging capacity shows that constraints can arise after wafer fabrication. The power bottlenecks discussed by the IEA show that construction obstacles remain even after equipment leaves the factory.^[16]^[15] This report’s assessment is that a shortage at a particular stage may give its suppliers greater pricing power, but that advantage must be reassessed as supply expands and customer demand changes.

Capacity takes time to build, while chip generations and customer workloads can change during construction. A shortage today does not guarantee strong utilization once an expansion is complete. Buyers need to assess delivery dates and readiness across the whole project; suppliers need to judge whether demand will persist when their new capacity comes online.

2. Revenue growth and investment returns

The table below selects public figures from different stages of the value chain to show where demand is turning into revenue. Companies differ in fiscal periods, product scope and revenue recognition. These figures therefore do not rank shares of a single market. All amounts are in billions of US dollars and represent disclosed quarterly revenue; orders and forecasts are excluded.

Company / business	Period ended	Quarterly revenue ($bn)	Scope and source
NVIDIA Data Center	2026-07-26	89.0	Includes computing and networking; not GPU revenue alone.^[18]
AMD Data Center	2026-06-27	6.7	Includes EPYC CPUs and Instinct GPUs.^[19]
Broadcom AI semiconductors	2026-08-02	16.7	Includes custom accelerators and AI networking.^[20]
TSMC , company-wide	2026-06-30	40.20	Includes non-AI demand, such as smartphones.^[16]
Dell AI-optimized servers	2026-07-31	16.4	Recognized server revenue.^[23]
Vertiv , company-wide	2026-06-30	Approx. 3.274	Includes infrastructure and services for non-AI uses.^[24]
Google Cloud	2026-06-30	24.768	Includes revenue from GCP, Workspace and other products.^[25]
CoreWeave , company-wide	2026-06-30	2.575	Company revenue, including cloud services.^[26]

NVIDIA offers a view of revenue concentration within one company. In the quarter ended July 26, 2026, Data Center revenue was approximately $89.0 billion against total company revenue of $96.221 billion. Data Center therefore represented approximately 92.5% of NVIDIA’s revenue, with other businesses accounting for the remaining 7.5%. These calculated percentages describe NVIDIA’s revenue mix; Data Center includes computing and networking, and the figures do not measure AI revenue alone or NVIDIA’s share of the industry.^[18]

REVENUE MIX · FY2027 Q2

Quarter ended July 26, 2026. Data Center as a share of NVIDIA's total quarterly revenue. This measures one company's revenue composition, not its industry market share or AI-only sales.

Worldwide company revenue · Share of NVIDIA revenue (%)

View the data table

NVIDIA revenue mix · FY2027 Q2 · Share of NVIDIA revenue (%)
Business grouping	Share
Data Center	92.5%
All other businesses	7.5%

Download data (CSV)

Calculated from approximately $89.0 billion in Data Center revenue and $96.221 billion in total revenue. Data Center share = 89.0 / 96.221 × 100, rounded to one decimal place; the other category is the residual to 100%. Data Center includes computing and networking and is not synonymous with AI. The source rounds Data Center revenue, so the percentages are approximate.

Source: NVIDIA — Financial results for second quarter fiscal 2027 (2026-08-26). Reviewed 2026-10-01.

Differences in scale do not establish which business model is more profitable. Chip design, wafer fabrication, complete-system delivery and cloud operations carry different costs. Assessing the quality of a business also requires examining gross profit, capital expenditure, cash flow and asset utilization. In particular, business revenue that includes CPUs or enterprise productivity services cannot all be counted as AI accelerator or model-service revenue.

Contract value is no substitute for profitability. In the second quarter of 2026, CoreWeave reported revenue of $2.575 billion alongside a GAAP net loss of $0.626 billion. Its approximately $104 billion quarter-end revenue backlog included remaining performance obligations and estimated future revenue under other contracts. Realization remained subject to conditions including delivery and service availability.^[26] These figures place growth and cost pressures on the same set of accounts.

3. Platform choice and software migration

The first approach is to build a hardware and software platform around accelerators. NVIDIA’s business now spans computing and networking, while AMD supplies both data center CPUs and accelerators. The second is for cloud providers to develop chips around their own workloads, then supply computing capacity to internal operations or external customers. Products from AWS and Google illustrate this approach. The third is to provide custom accelerators and networking chips for large customers. Broadcom’s disclosed AI semiconductor revenue falls into this category.^[18]^[19]^[20]^[21]^[22]

All three approaches can appear on a single customer’s purchasing list. An established platform is attractive when models are still changing and there is little time for migration. Specialized designs become more attractive when workloads are stable enough and usage is sufficiently large. This report therefore expects competition to center on workloads, software compatibility and total cost of use. A single chip metric is unlikely to determine the outcome.

Competition in China’s market also involves software. Huawei’s documentation positions CANN, its heterogeneous computing architecture, between AI frameworks and Ascend hardware, covering functions such as compilation, operators and runtime execution.^[27] Assessing a platform therefore requires looking beyond chip specifications to whether existing models can be migrated, which operators need rewriting and how easily the tools support debugging.

4. Hardware specifications and actual service costs

A useful system comparison starts with the same task. The model, precision, quality target and latency requirements need to be specified before throughput is compared. MLPerf’s inference benchmarks use defined scenarios and quality requirements for this reason.^[28] A chip specification or a result from one workload cannot establish the operating performance of every deployment.

For operators, the next step is to connect those measurements to the bill. The same number of installed machines can produce different costs per completed request if utilization, downtime or software efficiency differs. Evaluation therefore needs to include deployment work, power, maintenance and the amount of capacity customers actually use.

5. Whether paid usage can sustain expansion

On the demand side, watch whether paid usage keeps pace with capacity additions. On the supply side, track whether advanced packaging, memory and power projects are delivered on schedule. For operating performance, examine utilization, cash flow and investment payback periods. These measures are connected: delivery delays can hold back real customer demand, while fully installed equipment can still face falling prices and low utilization.

AI infrastructure now links model development with manufacturing, engineering and ongoing operations. Companies that deliver reliably, enable customers to use their products or services successfully, and cover costs while generating recurring cash flow at their own stage of the chain have an opportunity to turn a wave of purchasing into a lasting business. That is this report’s overall assessment of the value chain; actual delivery and financial results will be needed to test it.

Appendix: Supporting Materials

Source numbers correspond to the citations in the article. The appendix is separate from Parts 1 to 4.

[1] Early AI documents

Location: Turing, pp. 433–434; opening of the Dartmouth proposal; Dartmouth history page. Original papers and institutional records.

[2] AI winters and expert systems

Ted E. Senator (2026) Implications for AI Research: Applying Lessons from the Expert Systems Boom and Bust to the Current Large-Language Model Boom

Location: PDF pp. 1–2. A retrospective scholarly paper.

[3] Deep Blue

Campbell, Hoane & Hsu (2002) — Deep Blue

Location: IBM paper abstract. An account by the project researchers.

[4] GPUs and CUDA

Location: guide introduction and official historical account. Distinguishes the 2006 architecture introduction from the 2007 software release.

[5] Early AWS services

AWS Our Origins

Location: paragraphs on the launch of S3 and EC2. Official historical account.

[6] AlexNet

Krizhevsky, Sutskever & Hinton (2012) — ImageNet Classification with Deep Convolutional Neural Networks

Location: Sections 3 and 6, Table 2. Training hardware refers to an individual network; the competition score is for an ensemble.

[7] Historical training compute

Amodei & Hernandez / OpenAI (2018) — AI and Compute

Location: opening and Overview. Original 2018 analysis of its historical sample.

[8] Volta and Tensor Cores

NVIDIA (2017) NVIDIA Launches Revolutionary Volta GPU Platform

Official announcement, 2017-05-10. Used for the launch date and matrix-computation function.

[9] First-generation TPU

Jouppi et al. (2017) — In-Datacenter Performance Analysis of a Tensor Processing Unit

Location: paper abstract. Supports deployment in 2015 and its inference role.

[10] Transformer

Vaswani et al. (2017) — Attention Is All You Need

Location: abstract and Section 4. Findings relate to the paper’s machine-translation experiments.

[11] GPT-3 and ChatGPT

Location: GPT-3 abstract and ChatGPT launch page. A model paper and the product announcement of 2022-11-30, respectively.

[12] Llama 3 training cluster

Meta Llama Team (2024) — The Llama 3 Herd of Models

Location: Sections 3.3.1–3.3.4. An engineering example from a particular training project.

[13] Cooling configurations

Location: GB200 NVL72 rack description and H100 Form Factor specification. Evidence for the named product configurations.

[14] PagedAttention

Kwon et al. (2023) — Efficient Memory Management for Large Language Model Serving with PagedAttention

Location: abstract and evaluation. Throughput findings depend on the tested models, workloads and latency constraints.

[15] Data center electricity

IEA (2026) — Key Questions on Energy and AI: Executive Summary

Institutional report, 2026-04-16; executive summary. 485 TWh is a 2025 estimate and 950 TWh a 2030 forecast; both include non-AI uses.

[16] TSMC: fabrication and packaging

Location: technology page; presentation p. 4; call transcript p. 10. Revenue is company-wide; the packaging constraint is management’s assessment at that time.

[17] HBM product specifications

Micron — HBM4

Location: specifications for the 12-high product. Capacity and bandwidth are supplier component specifications, not measured server performance.

[18] NVIDIA quarterly revenue

NVIDIA — Q2 fiscal 2027 results (2026-08-26)

Location: Data Center discussion and the quarter ended 2026-07-26. The revenue covers computing, networking and other products in that business.

[19] AMD quarterly revenue

AMD — Q2 2026 financial results (2026-08-04)

Location: Data Center discussion; quarter ended 2026-06-27. The segment includes server CPUs and GPUs.

[20] Broadcom quarterly revenue

Broadcom — Q3 fiscal 2026 results (2026-09-02)

Location: AI semiconductor revenue discussion; quarter ended 2026-08-02. Uses reported revenue, not guidance for the following quarter.

[21] AWS custom silicon

AWS — Amazon EC2 Trn3 UltraServers availability (2025-12-02)

Official availability announcement. Supports availability, not deployment volume or market share.

[22] Google TPU products

Google — Introducing TPU 8t and TPU 8i (2026-04-22)

Official product introduction. Supports workload specialization, not general availability or installed volumes.

[23] Dell: revenue, orders and backlog

Dell — Q2 fiscal 2027 financial results (2026-09-01)

Location: AI server commentary and the quarter ended 2026-07-31. Revenue, orders and backlog are cited as separate measures.

[24] Vertiv: power and thermal management

Vertiv — Q2 2026 results, SEC Exhibit 99.1 (2026-07-29)

Location: net sales and company description; quarter ended 2026-06-30. Figures are company-wide.

[25] Google Cloud revenue scope

Location: release segment-revenue table; Google Cloud in the 10-Q revenue-recognition discussion. Includes cloud services, subscriptions and product sales.

[26] CoreWeave: growth and operating costs

CoreWeave — Q2 2026 earnings release (2026-08-11)

Location: highlights, revenue-backlog definition and income statement; quarter ended 2026-06-30. Net loss is GAAP; backlog is not cash received.

[27] Ascend software architecture

Huawei — CANN Community Edition 8.5.0 documentation

Location: CANN architecture and functionality. Technical documentation, not comparable market-share evidence.

[28] Conditions for inference comparisons

MLCommons — MLPerf Inference: Datacenter

Location: benchmark description, scenarios and quality requirements. Used for comparison principles, not vendor rankings.

[29] ASE advanced packaging

ASE — VIPack™

Location: VIPack overview and six packaging technology pillars, especially the passages on 2.5D/3D architectures and HBM interconnects.

[30] SK hynix high bandwidth memory

SK hynix Begins Volume Production of Industry’s First HBM3E (2024-03-19)

Location: Opening paragraph of the 19 March 2024 release, the HBM definition and the discussion of AI processor–memory interconnections.

[31] Samsung high bandwidth memory

Samsung Semiconductor — HBM

Location: HBM overview describing TSV stacking, AI training and HPC; used to establish business scope, not customer qualification or market share.

[32] Supermicro GPU servers

Supermicro — GPU Servers for AI, Deep / Machine Learning & HPC

Location: The Liquid Cooled GPU Systems and Air Cooled GPU Systems categories under Supermicro GPU Servers.

[33] Schneider Electric data center infrastructure

Schneider Electric — AI Data Centers e-guide (2026-02-11)

Location: Opening portfolio description on the guide download page; version 1.5, document 998-2372985_AI_Ready_DC.

[34] Microsoft Azure accelerated computing

Microsoft Azure — Virtual Machine series

Location: The N Family — GPU accelerated virtual machines section, including the roles of the ND, NC and NV series.

Brand icon sources and licenses are listed in the asset credits.

Semiconductors and Chips: Industry History, Value Chain, Markets, and Risks

Mon, 28 Sep 2026 00:00:00 +0000

Scope and Data Notes

In this report, the “semiconductor industry” includes chip design, electronic design automation (EDA) software and semiconductor intellectual property (IP), manufacturing equipment and materials, wafer fabrication, packaging and testing, and major end uses. Historical events are dated to when they occurred. Company financials, capacity, and process developments generally reflect information through December 31, 2025; policy information is updated through September 27, 2026. Market-share figures are cited only when the source specifies the market boundary, time period, and measurement basis. Definitions of “foundry,” “AI accelerator,” and “advanced process” vary across organizations, so figures using different definitions should not be compared directly.

Executive Summary

Semiconductors are not a single market. They are a cross-border industrial network spanning design tools, architecture and circuit IP, manufacturing equipment, critical materials, wafer fabrication, packaging and testing, and end systems. Development cycles, capital needs, and business models differ substantially across these activities. Software and IP businesses depend on research, ecosystem compatibility, and long-term licensing relationships. Equipment and materials require lengthy process qualification. Wafer fabrication relies on sustained capital investment, yield learning, and capacity utilization. Packaging and testing are expanding from conventional back-end services into system-level integration. A single “smile curve” or industry-wide gross-margin range cannot adequately describe this structure.

Three forces have shaped the industry over the past eight decades. The first is progress in devices and manufacturing, from the transistor, integrated circuit, and planar process to FinFETs, gate-all-around transistors, and extreme ultraviolet (EUV) lithography. The second is a change in industrial organization. The rise of the dedicated foundry allowed design and manufacturing to be performed by different companies, supporting a specialized ecosystem of fabless designers, foundries, outsourced assembly and test providers (OSATs), and tool suppliers. The third is a shift in demand, from mainframes and consumer electronics to personal computers, mobile communications, cloud computing, automotive electronics, and today’s AI infrastructure.

By the end of 2025, AI training and inference demand was driving investment in advanced logic, advanced packaging, high-bandwidth memory (HBM), and high-speed interconnects. That growth, however, was not reaching every semiconductor category equally. Mature-node chips, analog and power devices, consumer memory, and industrial semiconductors remained subject to their own inventory cycles and end-market demand. Governments were also using incentives, research programs, and export controls to strengthen supply security. As a result, supply-chain decisions increasingly balance cost and scale against compliance, regional capacity, and resilience.

1. How the Industry Developed

1.1 From Vacuum Tubes to Silicon Transistors

Electronic computers of the 1940s relied heavily on vacuum tubes. Tubes could amplify and switch electrical signals, but their size, power consumption, heat, and limited service life constrained miniaturization and reliability. In 1947, a Bell Laboratories team developed the point-contact transistor, establishing solid-state devices as a promising alternative.H18

Early transistors were mainly made of germanium. In 1954, Morris Tanenbaum at Bell Laboratories produced a silicon transistor, while a Texas Instruments team led by Gordon Teal produced the first commercial silicon transistors. Silicon eventually prevailed not only because of its high-temperature performance and availability, but also because its interface with silicon dioxide permits a stable insulating layer and repeatable, scalable manufacturing processes.H01

In 1957, eight engineers left Shockley Semiconductor Laboratory to establish Fairchild Semiconductor. Fairchild and the companies that grew out of it became an important part of Silicon Valley’s semiconductor startup network. The defensible conclusion is that this event accelerated the circulation of technical talent, venture capital, and new firms; it was not the sole origin of Silicon Valley’s entrepreneurial culture.

One of the key Bell Laboratories patents associated with the point-contact transistor is John Bardeen and Walter Brattain’s US 2,524,035, Three-Electrode Circuit Element Utilizing Semiconductive Materials.H15 Its patent grant date is distinct from the 1947 laboratory demonstration.

1.2 Integrated Circuits, the Planar Process, and Moore’s Law

Replacing vacuum tubes with individual transistors did not solve the problems of connecting large numbers of components or manufacturing them at scale. Integrated circuits and the planar process emerged in the late 1950s. Through oxidation, photolithography, diffusion, and metal interconnection, the planar process made it possible to form and connect multiple devices on the surface of a single silicon wafer. It laid the foundation for high-volume monolithic integrated circuits.

Early integrated circuits took different technical approaches. Jack Kilby’s relevant patent is US 3,138,743, Miniaturized Electronic Circuits. Robert Noyce’s is US 2,981,877, Semiconductor Device-and-Lead Structure.H16 H17

In 1965, Gordon Moore used the limited data then available to predict that the number of components on an integrated circuit would roughly double every year for the next decade. In 1975, he revised the cadence to approximately every two years.H02 What became known as “Moore’s Law” was both an empirical observation and a reference point for coordinating technology roadmaps across design, equipment, materials, and manufacturing. It does not imply that the price of every chip automatically falls. Whether the cost per function declines also depends on die area, yield, design complexity, packaging, and utilization.

1.3 Microprocessors, Memory Competition, and US–Japan Adjustments

Intel introduced the 4004 in 1971. Developed for a calculator, it was a commercial four-bit microprocessor containing approximately 2,300 transistors.H03 Its significance lay in showing that a general-purpose programmable processor could be sold as a standardized product. The personal-computer market subsequently emerged through the combined development of eight- and 16-bit processors, memory, software, and complete computer systems. The 4004 alone did not “directly launch the PC era.”

From the late 1970s through the 1980s, DRAM became a focal point of competition between Japanese and US companies. Japan’s Ministry of International Trade and Industry supported a VLSI research program, while manufacturers’ production capabilities, quality control, and domestic electronics demand also contributed to their growth.H14 A historical study by the US International Trade Commission reports that Japanese firms’ share of the global DRAM market rose from less than 30% in 1978 to nearly 75% in 1986.H04 Those dated figures are more precise than a general claim of “nearly 80% in the mid-1980s.”

Facing price competition in memory, Intel exited DRAM around 1985 and redirected resources to microprocessors. Its consumer-facing Intel Inside cooperative marketing program formally began in 1991.H05 The 1986 US–Japan Semiconductor Agreement primarily addressed access to the Japanese market and anti-dumping concerns. Later arrangements referred to an industry expectation that foreign suppliers would reach a 20% share of the Japanese market, not a binding floor reserved for US chips.H06

1.4 Dedicated Foundries and Vertical Specialization

Vertically integrated manufacturers dominated the industry’s early years, often handling product definition, design, wafer fabrication, packaging, and testing within one company. It would nevertheless be inaccurate to say that all companies followed the integrated device manufacturer (IDM) model. Specialization expanded as process development and fab construction became more expensive.

TSMC was founded in 1987 and built its business around a dedicated foundry model: it manufactured customers’ designs without selling its own branded chips.H07 This model enabled design companies to bring products to market without building advanced fabs, while foundries aggregated demand from multiple customers to spread process R&D and capacity investment. It created more room for fabless companies such as Qualcomm, NVIDIA, and Broadcom. AMD moved toward a fabless model much later, after spinning off manufacturing assets to GlobalFoundries in 2009–2010.H08

1.5 Immersion Lithography, FinFETs, and EUV

In the early 2000s, the industry faced growing pressure to improve the resolution of 193 nm argon-fluoride (ArF) lithography. A 157 nm exposure path had been explored, but it posed challenges for materials and optical systems. Immersion lithography placed ultrapure water between the projection lens and wafer, increasing numerical aperture and improving resolution and depth of focus while retaining the 193 nm light source. The wavelength remained 193 nm; resolution improved through the larger numerical aperture. In 2003, TSMC ordered the industry’s first immersion lithography tool from ASML.H19 Commercial production still required collaborative work across fabs, optics, light sources, photoresists, and research institutions.H09 S01

In transistor architecture, Hitachi researchers demonstrated a precursor to the FinFET in 1989. In the late 1990s, a University of California, Berkeley team involving Chenming Hu further developed and named the FinFET.H10 H13 Intel began high-volume production of its 22 nm tri-gate transistor in 2012.H11 FinFET is therefore best understood as the product of sustained research and industrialization by multiple teams, rather than the invention of a single researcher.

EUV lithography uses 13.5 nm light. ASML delivered its first production-oriented EUV system in 2013, and customers gradually adopted EUV for advanced logic and memory production later in the 2010s. The first High-NA EUV system was delivered in 2023.H12 Prices, configurations, and revenue-recognition practices differ significantly across system generations; any quoted equipment price must specify the model, year, currency, and accounting basis.

1.6 Mobile Computing, AI, and Heterogeneous Integration

Smartphones increased demand for highly integrated, low-power systems on a chip (SoCs), radio-frequency front ends, image sensors, and mobile memory. They also helped drive advanced manufacturing from planar transistors toward FinFETs. More recently, generative AI has shifted attention toward parallel computing, HBM, high-speed networks, and advanced packaging. GPUs are well suited to massively parallel workloads, but CPUs, GPUs, purpose-built accelerators, and network processors generally work together in a system. “GPUs replace CPUs” is too simple a description.

As the cost of designing and producing a single large die rises, chiplets and advanced packaging have become important ways to scale systems. A chiplet architecture does more than mechanically split a large logic chip. It assigns compute, input/output, cache, or analog functions to separately designed and manufactured dies, then integrates them through standard or proprietary interconnects. “More than Moore” is broader: it also encompasses the extension of functions such as sensing, radio frequency, power, optoelectronics, and heterogeneous materials. It should not be treated as synonymous with chiplets.

2. The Semiconductor Value Chain

INDUSTRY MAP

The semiconductor value chain

See how design, production capabilities and end markets fit together.

Read the full text outline

Semiconductors
- Upstream · Design & inputs
  - Chip design
    - CPUs, GPUs and accelerators
    - Analog, power and RF
  - EDA & reusable IP
    - Design and verification tools
    - Processor and interface IP
  - Equipment & materials
    - Lithography and process tools
    - Wafers, gases and chemicals
- Midstream · Production
  - Wafer fabrication
    - Dedicated foundries
    - Integrated device manufacturers
  - Assembly & packaging
    - Conventional packaging
    - Advanced packaging and chiplets
  - Testing
    - Wafer probing
    - Final test and reliability
- Downstream · End markets
  - Computing
    - Data centers and AI
    - PCs and smartphones
  - Connected systems
    - Automotive
    - Telecommunications
  - Specialized applications
    - Industrial and energy
    - Defense and aerospace

DEX editorial map based on the accompanying report. Examples are illustrative, not exhaustive or ranked. Companies can operate across several stages; connections show categories, not verified supplier contracts.

Sources: Semiconductor industry primer — production stages. Reviewed 2026-09-29.

2.1 Chip Design, EDA, and Semiconductor IP

Chip design begins with product requirements and system architecture, then proceeds through logic design, functional verification, synthesis, placement and routing, timing closure, physical verification, and tape-out preparation. EDA software links design rules, foundry process design kits, and manufacturing constraints. Its value comes from algorithms, complete tool flows, process compatibility, and years of accumulated validation data.

Semiconductor IP consists of designed and verified modules that can be reused in a chip, including processor cores, memory controllers, PCIe, DDR, USB, SerDes, and security blocks. An instruction set architecture (ISA) must be distinguished from processor IP. Arm licenses both architectures and processor-core IP. RISC-V is an open-standard ISA, not a processor core that can be manufactured directly; companies must still develop or license a specific implementation.S02 x86 is a proprietary ISA ecosystem, with Intel and AMD as its principal product suppliers.

Digital devices include CPUs, GPUs, microcontrollers, FPGAs, SoCs, network processors, and AI accelerators. Analog and mixed-signal chips manage power, data conversion, amplification, and sensor interfaces. RF and optoelectronic devices handle wireless transmission and reception, filtering, power amplification, and conversion between electrical and optical signals. These categories differ in design cycle, software dependence, product life, and process needs. An advanced node is not the only measure of a chip’s value.

2.2 Manufacturing Equipment and Materials

Front-end equipment includes lithography, etching, thin-film deposition, ion implantation, thermal processing, cleaning, chemical-mechanical polishing (CMP), metrology, and defect inspection systems. Back-end equipment includes thinning and dicing, die attach, bonding, molding, probe systems, automatic test equipment (ATE), and sorting equipment. Atomic layer deposition (ALD) is especially useful for thickness control and conformal coverage in high-aspect-ratio structures. “High selectivity” applies to particular selective deposition processes, not to every ALD tool.

Critical materials include silicon wafers and compound-semiconductor substrates, photoresists, masks, electronic gases, wet chemicals, deposition precursors, CMP consumables, sputtering targets, package substrates, and bonding materials. Purity specifications vary by material and process; they cannot all be summarized as “nine nines.” In gas classification, phosphine, arsine, and diborane can be used for doping. Nitrogen trifluoride is primarily used for chamber cleaning and some etching processes, rather than as a typical dopant gas.

Qualification for high-volume production often takes substantial time. A supplier must demonstrate more than the specifications of a single tool or material batch: customers also need stable performance across lots, defect control, service capability, and compatibility with their process platform. This joint optimization helps explain high concentration in some niches. It does not mean that every segment has only one supplier.

2.3 Wafer Fabrication

Wafer manufacturers are commonly divided into IDMs and foundries. An IDM sells its own products and performs at least some manufacturing; a dedicated foundry primarily manufactures customer designs. In practice, the boundary is not absolute. Some IDMs offer foundry services to external customers, while some systems companies take a direct role in chip design and supply-chain management.

A typical front-end process repeatedly applies film formation, photoresist coating, exposure, development, etching, ion implantation, thermal processing, cleaning, and CMP to form transistors and multiple interconnect layers on a wafer. After front-end fabrication, a foundry delivers a processed wafer or diced dies, not a “bare wafer.” A bare wafer is generally a substrate on which device structures have not yet been formed.

Process-node names identify generations of manufacturing platforms; they no longer correspond to a single directly measurable physical dimension. “2 nm” or “Intel 18A” therefore does not mean that every transistor feature measures 2 nm or 1.8 nm. Process capability should be assessed through transistor architecture, density, performance, power, yield, design rules, and production status. Intel 18A uses RibbonFET gate-all-around transistors and PowerVia backside power delivery. In 2025, Intel disclosed that the first 18A client product had entered production and that it planned to begin high-volume production that year.S03 S06

2.4 Packaging and Testing

Conventional packaging protects the die, provides electrical and mechanical connections, and supports assembly into a system. Advanced packaging also enables dense interconnects, more bandwidth, power management, and heterogeneous integration. Flip-chip packaging connects a die to its substrate through bumps. In 2.5D packaging, a silicon interposer or redistribution structure can connect multiple side-by-side dies. In 3D packaging, dies are stacked using hybrid bonding, through-silicon vias (TSVs), or other vertical interconnects. CoWoS is a 2.5D and related advanced-packaging platform; it should not be conflated with every form of 3D stacking.

HBM typically stacks multiple DRAM dies connected by TSVs and integrates them with a logic chip for high bandwidth. 3D NAND, by contrast, stacks memory cells vertically within a NAND device. It is a device structure and manufacturing process, not a synonym for TSV-based die stacking.S04

Testing includes wafer-level probing, final testing after packaging, and reliability evaluation for particular uses. Automotive integrated circuits commonly undergo failure-mechanism-based stress tests and customer qualification under specifications such as AEC-Q100. These specifications are not equivalent to a “certification certificate” issued by a single organization.S05

2.5 End Markets

Data centers use CPUs, GPUs and dedicated accelerators, HBM, network switches and optical interconnects, power-management devices, and security chips. Smartphones and PCs balance performance, energy use, wireless connectivity, and cost. Automotive electronics encompass microcontrollers, analog and power devices, cockpit and driver-assistance processors, sensors, and battery-management chips; they also require lengthy qualification and supply commitments. Industrial, renewable-energy, telecommunications, and defense applications place particular weight on reliability, long-term supply, environmental tolerance, or specific security requirements.

Advanced nodes are not essential for every application. Power management, analog, RF, sensors, and many automotive and industrial products continue to use mature processes extensively. An industry assessment should therefore track both advanced-node investment and mature-node inventories, utilization, and replacement demand.

3. Market Structure

3.1 Concentration and Interdependence

Some semiconductor segments are highly concentrated because R&D is expensive, customer qualification takes time, process knowledge is difficult to replicate quickly, and software and hardware ecosystems raise switching costs. That does not establish that the top three suppliers hold 70%–90% in “almost every” subsector. A sound market-share statement first defines the market—for example, complete EUV systems, discrete data-center GPUs, DRAM, foundry services, or OSAT—and then specifies the geography, period, and whether it measures revenue or shipments.

Regional specialization likewise cannot be reduced to closed “blocs.” US companies are strong in EDA, processor and accelerator design, and parts of the equipment market. Europe is prominent in lithography, optics, and certain automotive and industrial chips. Japan has important materials, equipment, and image-sensor companies. South Korea has large-scale memory producers. Taiwan plays a central role in foundry and packaging. Mainland China is expanding its mature-process, packaging, equipment, and materials capabilities. Cross-border investment, customer relationships, and supply dependencies remain extensive.

3.2 Chip Design and AI Computing

General-purpose processors, mobile SoCs, analog chips, and AI accelerators each have different competitive structures. NVIDIA leads in data-center GPUs and their software ecosystem, but a claim that it holds 80%–90% of “AI training and inference chips” lacks a consistent market boundary. In its review of NVIDIA’s proposed acquisition of Run:ai, the European Commission estimated that NVIDIA’s shipment share of the defined global discrete data-center GPU market had exceeded 80%–90% in several preceding years and stood at 70%–80% in the first half of 2024. The decision also cautioned that shipment estimates inferred from revenue and average selling prices were less reliable.M01 The case illustrates why market share must be reported with its product scope, date, and method.

AMD and Intel offer GPUs or other accelerators, while cloud providers develop in-house or custom ASICs such as TPUs and Trainium. In-house chips can improve performance, cost, or supply control for specific workloads, but they do not automatically displace commercial GPUs. Their results depend on software tools, utilization, model fit, networking, and deployment scale.

3.3 Foundries and Advanced Processes

MARKET SHARE · Q4 2025

Wafer foundry revenue under TrendForce's market definition. Samsung excludes System LSI. This is not total semiconductor revenue or the expanded Foundry 2.0 market.

Worldwide · Share of foundry revenue (%)

View the data table

Global wafer foundry revenue share · Q4 2025 · Share of foundry revenue (%)
Company	Share
TSMC	70.4%
Samsung Foundry	7.1%
SMIC	5.2%
UMC	4.2%
GlobalFoundries	3.8%
Other foundries	9.3%

Download data (CSV)

Five largest suppliers shown. Other foundries = 100% minus the five published shares and includes both other ranked and unranked suppliers. Percentages retain the source rounding. Historical quarter; not full-year 2025, all chip sales, or the broader Foundry 2.0 definition.

Source: TrendForce — AI Demand Drives 4Q25 Global Top 10 Foundries Revenue Up 2.6% QoQ; Samsung Gains Share and Tower Moves Up in Rankings (2026-03-12). Reviewed 2026-09-29.

TSMC is the leading dedicated foundry. In its 2025 annual report, the company defined “Foundry 2.0” broadly to include logic wafer fabrication, packaging, testing, masks, and non-memory IDM activity, and estimated that market at US$305 billion in 2025. This is substantially broader than conventional dedicated foundry services; a Foundry 2.0 share should not be directly compared with a third-party pure-foundry share. TSMC also reported that its 3 nm process accounted for 24% of its own wafer revenue in 2025 and that its 2 nm process entered volume production in the fourth quarter of that year.M02 Those figures describe TSMC’s revenue mix and manufacturing progress, not the entire industry’s 3 nm or 2 nm market share.

Samsung operates in memory, logic products, and foundry services, so its process investment must be considered alongside both internal IDM demand and external foundry customers. Intel offers manufacturing and packaging to external customers through Intel Foundry; the scale of 18A production and external customer adoption should be updated against subsequent earnings reports and product deliveries. SMIC, UMC, and GlobalFoundries also have different product mixes, process platforms, customer industries, and expansion priorities.

3.4 Memory and Advanced Packaging

The major DRAM suppliers include Samsung Electronics, SK hynix, and Micron. NAND participants also include Kioxia, Western Digital/SanDisk-related operations, and Solidigm. Memory is highly cyclical: prices respond to inventory, capital expenditure, product transitions, and end-market demand. HBM growth has prompted suppliers to invest in advanced DRAM, TSVs, and packaging. Any assertion that “two companies hold the overwhelming majority of HBM” should identify the quarter and whether it measures revenue or bit shipments, while accounting for changes at suppliers including Micron.

Foundries, memory makers, IDMs, and OSATs all participate in advanced packaging. ASE, Amkor, and JCET are major OSAT providers, while TSMC, Samsung, and Intel combine advanced packaging with front-end processes. Control is not simply shifting in one direction from OSATs to foundries. Platforms compete and overlap in interposers, hybrid bonding, HBM integration, testing, and volume delivery.

3.5 Equipment, Materials, and Profitability

ASML is currently the only company able to supply complete EUV lithography systems commercially. DUV, metrology, inspection, and other manufacturing-equipment markets have different competitors. ASML’s 2025 annual report records €32.7 billion in total net sales, a gross margin of 52.8%, and revenue recognition for 48 EUV systems during its 2025 fiscal year.M03 These figures illustrate the scale and technical barriers of the EUV business. They do not support a claim that every equipment monopoly earns a 60%–80% gross margin.

TSMC reported a gross margin of 59.9% for 2025. Revenue recognition, depreciation, and cost structures differ among EDA, IP, equipment, materials, foundries, and packaging and test providers.M02 Profitability should therefore be analyzed using specific companies and a consistent fiscal year and accounting basis. At minimum, software licenses, equipment sales, materials, manufacturing, and testing should be distinguished rather than assigned fixed margins across the value chain.

4. Principal Risks and Constraints

4.1 Industry Cycles and Concentrated AI Demand

AI infrastructure is increasing demand for advanced logic, HBM, advanced packaging, networks, and power devices, but semiconductors remain subject to inventory and capital-spending cycles. If cloud providers slow investment, relevant suppliers could face order revisions and lower utilization. If AI-related revenue and computing demand continue to grow, advanced capacity could remain tight in the near term. These are conditional scenarios, not grounds for declaring an inevitable “ROI cliff” or “profit collapse.”

AI capacity does not crowd out every traditional chip category in equal measure. Advanced GPUs and automotive microcontrollers generally use different nodes and production lines, limiting direct substitution. HBM expansion may redirect some DRAM resources, but consumer-memory prices also depend on inventory, demand, and suppliers’ capital discipline. Risk analysis needs to distinguish products and processes.

4.2 Industrial Policy, Export Controls, and Regionalization

The US CHIPS and Science Act provided the Department of Commerce with US$50 billion for manufacturing incentives, R&D, and related programs. That figure represents statutory program funding, not cash already paid to companies.R01 The European Chips Act took effect in September 2023. The EU set a policy goal of raising its share of the global semiconductor market to 20% by 2030; that number is a target, neither an achieved share nor a firm forecast.R02 In June 2026, the European Commission proposed a Chips Act 2.0 to build on the original law. The proposal should be distinguished from the 2023 act already in force.R05

Export controls are changing customer screening and delivery procedures for equipment, software, HBM, and advanced computing chips. In January 2025, the US Bureau of Industry and Security updated advanced-computing controls and foundry due-diligence requirements; related rules also changed definitions of advanced-node integrated circuits and the Entity List.R03 Businesses consequently face licensing, end-user, resale, technical-service, and geographic compliance risks. Policies can change, so a rule in force at one point should not be treated as a permanent industrial boundary.

Regional incentives can add local capabilities and geographic redundancy, but they can also raise construction costs, reduce utilization, intensify competition for talent, and complicate cross-border operations. Whether a project amounts to “duplicative capacity” depends on actual demand, its technology generation, and long-term utilization. Not every localization project can be assumed in advance to destroy economies of scale.

4.3 Technical Complexity and Recovery of Capital Investment

Advanced processes face short-channel effects, interconnect delay, power density, heat, stochastic defects, and growing design complexity. Gate-all-around transistors, backside power delivery, EUV, High-NA EUV, and advanced packaging offer new ways to scale, while increasing R&D, equipment, mask, design-migration, and yield-ramp costs. A node label is not a physical-limit gauge. The characters “2 nm” alone cannot establish that quantum tunneling has become the decisive obstacle for every product.

Investment in a fab or critical tool varies substantially with the project boundary, cleanroom, equipment mix, capacity, and location. A claim that a fab costs US$20–30 billion, or that a certain tool has a particular price, should identify a specific project or system, announcement date, currency, and whether infrastructure is included. Totals from different projects should not be substituted for one another.

4.4 Supply Concentration and Operational Continuity

Concentrated supply does create single-point risks. ASML is currently the sole commercial supplier of complete EUV systems, and some equipment subsystems, material formulations, and advanced-packaging capacities are concentrated among a small number of firms. Yet photoresists, metrology and inspection, and most process materials generally have multiple suppliers—even if an alternative cannot be qualified and substituted quickly. More useful risk measures include qualification time for replacements, inventory coverage, geographic concentration, capacity flexibility, and the cost of an alternative process. A blanket claim that there is “no second option anywhere in the world” obscures these differences.

Companies can reduce exposure through developing second sources, stocking critical spare parts, diversifying production sites, signing long-term purchase agreements, and conducting joint qualification. Because semiconductor tools and materials must be qualified against specific processes, establishing an alternative often takes months or longer. That work should begin during normal operations, before a supply interruption.

4.5 Electricity, Water, and Infrastructure

Advanced fabs require reliable electricity, ultrapure water, gases, and waste-treatment systems. AI data centers are increasing demand for high-density computing, cooling, and grid connections. The International Energy Agency estimates that data centers used about 415 TWh of electricity worldwide in 2024, or about 1.5% of global electricity consumption. In its 2025 base case, the IEA projects roughly 945 TWh by 2030.R04 These are global model estimates; they do not mean that every regional grid will reach its limits at the same time.

Power constraints vary sharply by location, depending on grid-connection queues, generation mix, transmission and distribution capacity, and data-center clustering. Semiconductor companies should evaluate power reliability, water availability, extreme weather, and carbon costs when selecting sites. Data-center customers should also incorporate server utilization, model efficiency, and cooling methods into capacity planning.

4.6 Talent and Organizational Capability

Semiconductor production requires specialists in devices, materials, chemistry, mechanics, optics, software, quality, and equipment maintenance. New fabs need more than additional graduates: they need experienced teams that can introduce processes into volume production, improve yield, and keep tools running. Talent risk should not be described as an equally “severe shortage” in every region. It should be measured by project location, job category, hiring time, and turnover.

If industrial policy subsidizes buildings and machines without vocational training, research platforms, supplier engineering capacity, and arrangements for international talent mobility, new capital may be slow to turn into stable output. Companies should include training periods, succession for critical roles, replication across fabs, and supplier-service capacity in their expansion plans.

Conclusion

Technological accumulation, specialization, and cross-border collaboration define the semiconductor industry. Advances in transistor architecture, lithography, materials, design tools, fabrication, and packaging depend on one another. No single segment determines the outcome on its own. Dedicated foundries separated design and manufacturing, while advanced packaging is bringing front-end and back-end work closer together again. AI has increased demand for advanced computing, but has also deepened dependence on HBM, interconnects, electricity, and software ecosystems.

Assessing a company or market requires comparable definitions and data. A market-share figure needs a time period, geography, product boundary, and measurement basis. An equipment price needs a model and year. A process node cannot be read as a literal physical dimension. Gross margins should be compared only under consistent accounting conventions. Unpublished yields, customer confidence, or future capacity should not be presented as established facts.

Over the next several years, competition will center on four capabilities: advancing device and system technologies; maintaining efficient volume production despite heavy capital spending; building auditable cross-border supply networks; and securing power, talent, and critical materials. Regionalization will increase the weight of compliance and redundancy in investment decisions without fully replacing global specialization. Companies that assess technology roadmaps, customer demand, capital discipline, and supply security together will be better placed to navigate both growth and cyclical volatility.

References

Historical Sources

[H01] Computer History Museum, “1954: Silicon Transistors Offer Superior Operating Characteristics.” https://www.computerhistory.org/siliconengine/silicon-transistors-offer-superior-operating-characteristics/

[H02] Intel, “Moore’s Law.” https://www.intel.com/content/www/us/en/newsroom/resources/moores-law.html

[H03] Intel, “The Chip that Changed the World.” https://newsroom.intel.com/opinion/the-chip-that-changed-the-world

[H04] U.S. International Trade Commission, “The South Korea-Japan Trade Dispute in Context: Semiconductor Manufacturing, Chemicals and Concentrated Supply Chains.” https://usitc.gov/sites/default/files/publications/332/working_papers/semiconductor_working_paper_corrected_103119.pdf

[H05] Intel, “Ingredient Branding: End User Marketing and Intel Inside.” https://www.intel.com/content/www/us/en/history/virtual-vault/articles/end-user-marketing-intel-inside.html

[H06] Office of the United States Trade Representative, “1996 National Trade Estimate—Japan: Semiconductors.” https://ustr.gov/archive/Document_Library/Reports_Publications/1996/1996_National_Trade_Estimate/1996_National_Trade_Estimate-Japan.html

[H07] TSMC, “2025 Annual Report—About TSMC.” https://investor.tsmc.com/static/annualReports/2025/english/index.html

[H08] AMD, “AMD Reports Fourth Quarter and Annual Results,” January 21, 2010. https://ir.amd.com/financial-information/sec-filings/content/0001193125-10-009806/dex991.htm

[H09] ASML, “How Immersion Lithography Saved Moore’s Law,” 2023. https://www.asml.com/en/company/stories/2023/how-immersion-lithography-saved-moores-law

[H10] University of California, Berkeley EECS, “History.” https://eecs.berkeley.edu/about/history/

[H11] Intel, “Moore’s Law: Fun Facts.” https://www.intel.com/content/www/us/en/history/history-moores-law-fun-facts-factsheet.html

[H12] ASML, “EUV Lithography Systems.” https://www.asml.com/en/products/euv-lithography-systems

[H13] IEEE Technology Navigator, “FinFETs.” https://technav.ieee.org/topic/finfets/

[H14] Ministry of Economy, Trade and Industry of Japan, “2018 White Paper on International Economy and Trade—VLSI Project History.” https://www.meti.go.jp/report/tsuhaku2018/2018honbun/i2220000.html

[H15] John Bardeen and Walter H. Brattain, US 2,524,035, “Three-Electrode Circuit Element Utilizing Semiconductive Materials.” https://patents.google.com/patent/US2524035A/en

[H16] Jack S. Kilby, US 3,138,743, “Miniaturized Electronic Circuits.” https://patents.google.com/patent/US3138743A/en

[H17] Robert N. Noyce, US 2,981,877, “Semiconductor Device-and-Lead Structure.” https://patents.google.com/patent/US2981877A/en

[H18] Computer History Museum, “1947: Invention of the Point-Contact Transistor.” https://www.computerhistory.org/siliconengine/invention-of-the-point-contact-transistor/

[H19] ASML, “TSMC Selects ASML for Industry’s First Immersion Tool Order,” December 3, 2003. https://www.asml.com/en/news/press-releases/2003/tsmc-selects-asml-for-industry-first-immersion-tool-order

Technology and Value-Chain Sources

[S01] ASML, “Lenses and Mirrors—Lithography Principles.” https://www.asml.com/technology/lithography-principles/lenses-and-mirrors

[S02] RISC-V International, “About RISC-V.” https://riscv.org/about/

[S03] Intel, “Intel 18A Process Technology Simply Explained,” January 30, 2025. https://newsroom.intel.com/intel-foundry/intel-18a-process-technology-simply-explained

[S04] Samsung Semiconductor, “3D V-NAND Flash Memory.” https://semiconductor.samsung.com/support/tools-resources/dictionary/semiconductor-glossary-3d-v-nand-flash-memory/

[S05] Automotive Electronics Council, “AEC-Q100: Failure Mechanism Based Stress Test Qualification for Integrated Circuits,” documents index. https://www.aecouncil.com/AECDocuments.html

[S06] Intel, “Postcard from Intel Technology Tour Arizona: Panther Lake Draws in Cameras and Crowds,” October 10, 2025. https://www.intel.com/content/www/us/en/newsroom/news/client-computing/postcard-itt-panther-lake-draws-cameras-and-crowds.html

Market and Company Sources

[M01] European Commission, Case M.11766, NVIDIA/Run:ai merger decision, 2024 market evidence. https://ec.europa.eu/competition/mergers/cases1/202516/M_11766_10599589_2740_3.pdf

[M02] TSMC, “2025 Annual Report.” https://investor.tsmc.com/static/annualReports/2025/english/index.html

[M03] ASML, “2025 Annual Report.” https://www.asml.com/en/investors/annual-report/2025

Policy and Risk Sources

[R01] U.S. Department of Commerce, “Semiconductor Industry—CHIPS for America.” https://www.commerce.gov/issues/semiconductor-industry

[R02] European Commission, “European Chips Act.” https://digital-strategy.ec.europa.eu/en/policies/european-chips-act

[R03] U.S. Bureau of Industry and Security, “Commerce Strengthens Restrictions on Advanced Computing Semiconductors,” January 15, 2025. https://www.bis.gov/press-release/commerce-strengthens-restrictions-advanced-computing-semiconductors-enhance-foundry-due-diligence-prevent

[R04] International Energy Agency, “Energy and AI,” April 10, 2025. https://www.iea.org/reports/energy-and-ai

[R05] European Commission, “Proposal for the Chips Act 2.0,” June 3, 2026. https://digital-strategy.ec.europa.eu/en/library/proposal-chips-act-20

Cybersecurity: An Industry Map From Network Defenses to Zero Trust

Tue, 11 Aug 2026 00:00:00 +0000

Part 1: Story

An often-repeated account describes attackers using a connected aquarium sensor as an entry point to a casino network. It illustrates how an overlooked device can expand a network’s attack surface.

The public retellings do not supply enough independently verifiable information to confirm the casino, date, defenses, or amount of data taken. Treat it as an illustrative anecdote, not a documented case study or a quantitative measure of cyber risk.

This story brings us to an important subject—

Welcome, I’m Dex. Welcome to my industry report. Before we dive in, let’s take a look at a brief history of the industry.

Part 2: Industry History

1970s: ARPANET and Creeper

Early networked experiments such as Creeper and Reaper are part of the history of self-propagating programs and countermeasures. Assigning a single unqualified “first worm” or “first antivirus” to either program obscures differences in definitions and surviving records.

1980s: Birth of Commercial Antivirus Software

Commercial antivirus products emerged in the 1980s, and their precise chronology depends on how a “first” product is defined. The transition from standalone personal computers to connected business networks expanded the range of threats and defenses.

Key Turning Point: Mid-1990s

During the 1990s, more connected personal computers and business networks created additional opportunities for malicious code, denial-of-service attacks, and intrusions. This is a directional overview rather than a complete chronology of named incidents.

2000s (2000–2009): Commercial and Organized Cybercrime

The 2000s marked a transitional period for cybersecurity threats, shifting from mere pranks to serious, organized, and commercially driven criminal activity. Driven by core threat data and landmark incidents, people began to realize the vulnerabilities inherent in the early digital age during this explosion of cybersecurity incidents:

Fast-spreading worms (2000–2004): Incidents such as ILOVEYOU and SQL Slammer showed how email and software vulnerabilities could cause rapid, widespread disruption. Exact global infection and loss estimates vary by source and method.
Rise of Commercial Cybercrime (Mid-to-Late 2000s): Hacker motivations shifted from technical boasting to economic gain.
- Botnets and data breaches: Compromised computers were increasingly used for spam and fraud, while payment-card incidents highlighted the costs of weak data protection. Incident totals and exposed-record counts require case-specific primary reports.
Distributed denial of service: High-profile incidents exposed the operational costs of making online services unavailable; dollar-loss estimates are not directly comparable between incidents.
Espionage and advanced intrusions: Public disclosures such as Operation Aurora increased attention to persistent, targeted threats; cyber espionage itself predated the incident.

2010 to Present: Cloud-Native & AI-Driven Era

Between 2010 and 2019, the global cybersecurity landscape evolved from simple virus defense to geopolitical cyber warfare, massive data breaches, and ransomware ecosystems (e.g., Stuxnet, Sony Pictures hack, WannaCry).

Since 2020, the industry has undergone profound transformation characterized by supply chain attacks, open-source vulnerabilities, critical infrastructure ransomware, and AI-driven threats. The industry spans nearly six decades of history.

Part 3: Industry Value Chain

INDUSTRY MAP

The cybersecurity value chain

Explore the foundations, products and services that connect security suppliers to customers.

Read the full text outline

Cybersecurity
- Upstream · Foundations
  - Cloud infrastructure
    - AWS
    - Microsoft Azure
    - Alibaba Cloud
  - Core components
    - Cryptographic libraries
    - Specialized chips
  - Threat intelligence
    - Indicators and telemetry
    - Threat-data feeds
- Midstream · Products
  - Endpoint & workloads
    - CrowdStrike
  - Network security
    - Palo Alto Networks
    - Fortinet
  - Identity & access
    - Okta
    - CyberArk
  - Security analytics
    - Splunk / Cisco
- Downstream · Delivery
  - Integration & resale
    - System integrators
    - Value-added resellers
  - Managed security
    - MSSPs
    - Customer security teams
  - Incident response
    - Mandiant
    - Consulting and response teams

Sources: Cybersecurity industry breakdown and source notes. Reviewed 2026-09-29.

Let’s briefly summarize the structure of the cybersecurity industry.

Upstream: Foundational Infrastructure & Threat Intelligence

The upstream sector serves as the cornerstone of the entire security industry, supplying midstream vendors with computing power, fundamental components, and critical threat intelligence:

Cloud Infrastructure & Computing Power: AWS, Microsoft Azure, and Alibaba Cloud are examples of infrastructure on which security services may run.
Foundational Core Components: Deep-tech companies mastering cryptographic algorithm libraries and high-precision processing chips (FPGAs, ASICs).
Threat Intelligence Providers: Acting as the “radar” of the industry. They gather Indicators of Compromise (IOCs) globally and package data feeds to power midstream security engines.

Midstream: Core Products & Solutions

Midstream vendors directly face hacker attacks and provide defensive tools to clients. Based on modern enterprise IT architecture, midstream is categorized into four major segments:

Endpoint & Workload Security: Antivirus, endpoint detection and response (EDR), and workload protection address different risks; CrowdStrike is one example of an EDR vendor.
Network & Perimeter Security: Firewalls, secure access service edge (SASE), and segmentation coexist; Palo Alto Networks and Fortinet are examples of suppliers.
Identity & Access Management (IAM): Identity is an important control alongside devices and networks, not the sole perimeter; Okta and CyberArk are examples of suppliers.
Security Operations & Data Analytics: Systems such as Splunk (acquired by Cisco) aggregate and investigate security events. Monitoring and analytics products differ in scope and are not interchangeable.

Downstream: Channels & Security Services

Because security products are complex, a massive downstream service market has emerged:

System Integrators & VARs: Service providers assisting enterprises with procurement, installation, and basic hardware configuration.
Managed Security Service Providers (MSSP): Addressing the global shortage of security engineers by directly managing enterprise security operations 24/7 on a subscription basis.
High-End Consulting & Incident Response: Teams like the Big Four or Mandiant providing penetration testing and emergency rescue during ransomware attacks.

Summary: Simply put, upstream provides materials and infrastructure; midstream builds weapons and trains troops; downstream handles tactical deployment and command.

Part 4: Industry Market Landscape

MARKET SHARE · Full year 2024

IDC modern endpoint security segment; not the whole cybersecurity market.

Worldwide · Share of modern endpoint security revenue (%)

View the data table

Modern endpoint security revenue share · Full year 2024 · Share of modern endpoint security revenue (%)
Company	Share
Microsoft	28.6%
Other	71.4%

Download data (CSV)

IDC estimates reproduced on a vendor's official website. Other is the residual share of all remaining suppliers. Revenue share does not measure customer counts or product effectiveness. Historical 2024 snapshot.

Source: IDC, reproduced by Microsoft — Microsoft ranked number one in modern endpoint security market share third year in a row (2025-08-27). Reviewed 2026-09-29.

There is no single comparable “cybersecurity market” figure without specifying geography, year, whether services and cloud infrastructure are included, and the research method. The supplied 2022 Menlo Ventures map identifies product categories and companies; it does not substantiate this article’s earlier $250B–$300B size, $500B forecast, CAGR, or vendor-share estimates. Those numbers have been removed pending a traceable dataset.

The global market is divided into four major camps:

1. Cross-Domain Tech Giants

Key Players: Microsoft (Defender / Sentinel), Google (Mandiant)
Competitive Moat: Leveraging software ecosystems and distribution to integrate security products.

2. Pure-Play Security “Big Three”

Key Players: Palo Alto Networks, CrowdStrike, Fortinet
Product focus: Palo Alto Networks sells network and cloud security; CrowdStrike emphasizes endpoint and cloud protection; Fortinet sells network-security appliances and software. These are illustrative positions, not audited share rankings.

3. Traditional IT & Hardware Giants

Key Players: Cisco, IBM, Trend Micro
Product focus: Enterprise networking and IT software, with acquisitions used to expand security portfolios.

4. Niche Specialists

Key Players: Zscaler (Zero Trust / SASE), Cloudflare (Edge Protection), Okta (Identity)
Competitive Moat: Dominating specific technical niches to attract top-tier enterprise clients.

Two Trends Shifting Market Dynamics

Vendor Consolidation: Some buyers prefer fewer integrations and vendors; the outcome depends on their existing architecture and procurement needs.
Cloud and AI: Cloud-delivered tools and automated detection are growing areas of investment, while hardware controls still serve important use cases.

Part 5: Industry Challenges & Bottlenecks

Despite intense competition, the industry faces fundamental challenges:

1. Asymmetric Warfare

Defenders must protect every single endpoint and password, whereas attackers need only find one weak link using AI tools. Defenders remain in a reactive cycle while AI drastically lowers attack costs and sky-rockets defense expenses.

2. Compliance-Driven “Shelfware”

Many non-critical enterprises buy security tools primarily to pass audits rather than stop hackers, creating a market flooded with “shelfware” installed for inspection and then ignored.

3. Tool Fragmentation & Alert Fatigue

Large organizations can struggle with overlapping tools and alert volumes. A universal average number of tools or false-positive rate would need a defined sample and measurement method.

Value Chain Bottlenecks

Upstream: Shared software components can create widespread exposure, as CISA’s Log4j advisories illustrate.
Midstream: Ongoing research, complex integrations and operational resistance can slow adoption of zero-trust approaches.
Downstream: Labor-intensive services face staffing and incident-response challenges; margins vary across businesses.

This competition appears to be a death spiral with no end in sight; as for how the cybersecurity industry will evolve—whether a super-giant akin to Google will emerge, or if the advent of AI will trigger a commercial tsunami—only time will tell.

That concludes my industry report. If you found it interesting, please like the video and subscribe to my channel. I’m Dex—see you next time.

Source notes and primary materials

NIST SP 800-207: Zero Trust Architecture (2020) — original standard supplied with the working materials. It defines an architectural approach, not market size or company share.
Menlo Ventures: Cybersecurity Market Map (2022) — the supplied category/company map, a 2022 snapshot rather than a 2026 revenue dataset or endorsement of the named vendors.
CISA: Apache Log4j vulnerability advisory — primary security guidance for the software-supply-chain example.

The accompanying Network Security document is a research reading list, not primary verification for the anonymous casino account or the removed market figures. The incident specifics remain unverified in public primary records.

View or download the supplied original

NIST SP 800-207: Zero Trust Architecture (2020)

Original PDF · National Institute of Standards and Technology, 59 pages

Open PDF in a new tab Download original PDF Publisher's copy

If the preview is unavailable in your browser, use “Open PDF in a new tab” above.

The Menlo Ventures Cybersecurity Market Map PDF is available directly from its publisher; it is not hosted here because permission to redistribute that copyrighted PDF has not been established.

Links contained in the Network Security research note

These are the supplied note’s research and video links. They have not all been independently verified and should not be read as endorsement or primary evidence. Links without Word hyperlink formatting have also been included.

Incident and industry background:

Market and technical references:

Video references from the note (third-party material, not licensed for reuse here):